1. Field of the Invention
The present invention relates to an oscillator, a voltage controlled oscillator using the oscillator, and a phase locked loop circuit using the voltage controlled oscillator. More particularly, the present invention relates to an oscillator including a plurality of delay elements which are connected in a ring shape, a voltage controlled oscillator including that oscillator which oscillates at a frequency corresponding to a control voltage, and a phase locked loop circuit including that voltage controlled oscillator which produces an internal clock signal in synchronization with an externally applied reference clock signal.
2. Description of the Background Art
FIG. 22 is a block diagram showing a structure of a conventional phase locked loop (hereinafter represented by the abbreviation PLL) circuit 200 such as the one described in an article by Deog-Kyoon Jeong et al. entitled "Design of PLL-Based Clock Generation Circuits," FIG. 2, in IEEE Journal of Solid-State Circuits, VOL. sc-22, No. 2 (April, 1987), pp. 255-261.
Referring to FIG. 22, this PLL circuit 200 includes a phase comparator 210, a charge pump+loop filter 220, a VCO circuit 230, a decoder+buffer 240, and a plurality of inverters 201 to 205.
Phase comparator 210 receives a reference clock signal REF which is amplified by inverters 201, 202 as well as an internal clock signal .phi.1 which is amplified by inverters 205, 203, and 204, and outputs control signals UP and DOWN corresponding to the phase difference between the received two clock signals REF and .phi.1. If the phase of internal clock signal .phi.1 lags behind reference clock signal REF, control signal UP is at "L" level and control signal DOWN is at "H" level. On the contrary, if the phase of internal clock signal .phi.1 precedes reference clock signal REF, control signal UP is at "H" level and control signal DOWN is at "L" level.
As shown in FIG. 23, charge pump+loop filter 220 includes a charge pump 220a and a loop filter 220b. Charge pump 220a includes inverters 221 to 223, a P channel MOS transistor 224 and an N channel MOS transistor 225. Loop filter 220b includes resistances 226, 227 and a capacitor 228. P channel MOS transistor 224 and N channel MOS transistor 225 are connected in series between a power supply terminal Vcc and a ground terminal GND. Control signal UP is input to the gate of P channel MOS transistor 224 via inverters 221 and 222 while control signal DOWN is input to the gate of N channel MOS transistor 225 via inverter 223. Resistances 226, 227 and capacitor 228 are connected in series between a ground terminal GND and a connection node N201 located between P channel MOS transistor 224 and N channel MOS transistor 225. A control voltage Vc is output from a connection node N202 between resistances 226 and 227.
When control signal UP is at "L" level and control signal DOWN is at "H" level, P channel MOS transistor 224 is turned on and N channel MOS transistor 225 is turned off. Charge current flows into capacitor 228 from power supply terminal Vcc through P channel MOS transistor 224 and resistances 226 and 227, and control voltage Vc is increased.
On the contrary, when control signal UP is in "H" level and control signal DOWN is in "L" level, N channel MOS transistor 225 is turned on and P channel MOS transistor 224 is turned off. Discharge current flows to ground terminal GND from capacitor 228 through resistances 227, 226 and N channel MOS transistor 225, so as to reduce control voltage Vc.
In other words, control voltage Vc is increased when the phase of internal clock signal .phi.1 lags behind reference clock signal REF, and is reduced when the phase of internal clock signal .phi.1 precedes reference clock signal REF.
In the above article, loop filter 220b is formed with separate components and independent from other circuits and is provided externally to the semiconductor chip.
Voltage controlled oscillator (hereinafter referred to as VCO circuit) 230 includes eight delay time variable inverters 231 to 238 and an ordinary inverter 239 connected in a ring shape, as shown in FIG. 24. Ordinary inverter 239 is provided so that delay time variable inverters 231 to 238 and inverter 239 will be odd-numbered in total.
Delay time (inverting time) of delay time variable inverters 231 to 238 varies depending on control voltage Vc of charge pump+loop filter 220. Inverting time of ordinary inverter 239 is set so that it is sufficiently shorter than the delay time of delay time variable inverters 231 to 238.
Accordingly, VCO circuit 230 will oscillate at a frequency corresponding to control voltage Vc, and clock signals C231 to C238 with a duty ratio of 50% as shown in FIG. 25(a) to (h) are output from output nodes of delay time variable inverters 231 to 238, respectively. Assuming that a single cycle of clock signals C231 to C238 is 360.degree., clock signals C232, C234, C236, and C238 are inverted delayed by 360.degree./16=22.5.degree. from clock signals C231, C233, C235, and C237, respectively.
Decoder+buffer 240 receives eight clock signals C231 to C238 from VCO circuit 230, amplifies them after a prescribed logic operation and outputs four non-overlapped signals .cent.1 to .cent.4. The logical product of signals C231 and C234 would be signal .phi.1 and the logical product of signals C235 and C238 would be signal .phi.2. The logical product of inverted signals C231 and C234 of signals C231 and C234 would be signal .phi.3 and the logical product of inverted signals C235 and C238 of signals C235 and C238 would be signal .phi.4. These signals .phi.1 to .phi.4 are employed as internal clock signals in the chip. Signal .phi.1 is amplified by inverter 205 and is output as an external clock signal OSC, and in addition, it is amplified by inverters 203 and 204 to be input to phase comparator 210.
If loop filter 220b, which is provided externally in the article described above, could be provided as an integrated circuit on the semiconductor chip, the external components for forming the loop filter 220b would be unnecessary so that the PLL circuit can be made more compact, made less expensive, and increased in its reliability.
However, as can be seen from chapter 3 of the above article, the condition for the stability of PLL circuit 200 is to satisfy the following equation (1): ##EQU1## where k=k.sub.0 R.sub.2 I.sub.p,
k.sub.0 is the gain (MHz/V) of VCO circuit 230, PA1 R.sub.2 is the resistance value (.OMEGA.) of resistance 227, PA1 I.sub.p is the current (A) of charge pump 220a, PA1 .omega..sub.i =2.pi.f.sub.i, PA1 f.sub.i is the frequency (Hz) of reference clock signal REF, PA1 .tau..sub.2 =R.sub.2 C, and PA1 td is the delay time (s) of decoder+buffer 240.
When this equation is analyzed, it is found that conditions for the stability of PLL circuit 200 may not be satisfied if loop filter 220b is provided on the semiconductor chip.
In the article, resistance value R.sub.1 of resistance 226 is 50 k.OMEGA., resistance value R.sub.1 of resistance 227 is 100 .OMEGA., capacitance C of capacitor 228 is 0.1 .mu.F (meaning that it is impossible to form this capacitor on the semiconductor chip), frequency f.sub.i of reference clock signal REF is 1 to 18 MHz (the rating value of which being 6.7 MHz), gain k.sub.0 of VCO circuit 230 is 12 MHz/V, and current I.sub.p of charge pump 220a is approximately (5-1.5)/50 k=70 .mu.A (assuming that supply voltage is 5 V). Accordingly, .tau..sub.2 =R.sub.2 C=100.times.0.1.times.10.sup.-6 =10 .mu.sec, and therefore, td/.tau..sub.2 in the above equation (1) can be substantially 0. In other words, since delay time td in the current integrated circuit is in the order of several tens of nano seconds at most, td/.tau..sub.2 would be approximately 10.sup.-3. Since td only appears in the term (1-td/.tau..sub.2) of the denominator of the above equation (1), td/.tau..sub.2 may be neglected.
When attempting to incorporate capacitor 228 of loop filter 220b into the integrated circuit, however, capacitance of the capacitor 228 which can be implemented at a reasonable cost would be about 100 pF at most. Accordingly, it is apparent that if td is 10 nsec, for example, then td/.tau..sub.2 =10.times.10.sup.-9 /100.times.1000.times.10.sup.-12 =1, meaning that td/.tau..sub.2 cannot be ignored.
When considering the equation only, it seems possible to increase resistance value R.sub.2 of resistance 227, but it is not preferable because it would cause an increase in the difference between control voltage Vc when charge pump 220b is on and off, and ripple will occur as a jitter which degrades the performance of PLL circuit 200. Therefore, it is clear that delay time td must be suppressed. Preferred value of td/.tau..sub.2 is about 0.1 or lower.
It is believed that buffer 242 of decoder+buffer 240 has the largest contribution to the occurrence of delay time td. As shown in FIG. 26, buffer 242 includes N inverters 242.1 to 242.N (N being a prime number) connected in series. As shown in FIG. 27, inverters 242.1 to 242.N each include a P channel MOS transistor 243 and an N channel MOS transistor 244 which are connected in series with one another between power supply terminal Vcc and ground terminal GND.
The number N of inverters 242.1 to 242.N constituting buffer 242 depends on magnitude of load capacitance. For example, when the load capacitance is 50 pF, the MOS transistor in inverter 242.N of the final stage requires a channel width W of about 100 .mu.m. In addition, it is believed that incrementing each channel width W so that it is 3 to 4 times larger than that of the previous stage, is most effective. Accordingly, if channel width W of an MOS transistor used for an ordinary internal gate is about 3 .mu.m, six inverters are required. Inverters 242.1 to 242.N in buffer 242 have delay time of around 1 nsec, respectively, in order to drive the inverter of the next stage which is larger than themselves. If a delay time of about 2 to 3 nsec has occurred at decoder 241, there would soon be a td of about 10 nsec. Therefore, stability of PLL circuit 200 would be less reliable.
In addition, stability of PLL circuit 200 is often presented by phase margin (PM) shown in the following equation (2). ##EQU2##
In the above article, the values of k.tau..sub.2 and td/.tau..sub.2 are as follows. ##EQU3##
When these values k.tau..sub.2 and td/.tau..sub.2 are inserted to the above equation (2), ##EQU4## and it can be understood that PLL circuit 200 will operate with stability.
However, if td/.tau..sub.2 is 1 when capacitor 228 is incorporated into the chip and buffer 242 having a high load driving capability is provided as in the above description, then PM&lt;.phi., and the operation of PLL circuit 200 would be unstable.
In addition, in the conventional PLL circuit 200, decoder 241 is indispensable in order to obtain a plurality of non-overlapped signals with a duty ratio of about 25%, which also has been preventing reduction in size and cost of the circuit.